• 专利标题:   Graphene FET comprises a gate stack including a seed layer, a gate oxide formed over the seed layer and a gate metal formed over the gate oxide, an insulating layer, a graphene sheet, a spacer, and a source contact and a drain contact.
  • 专利号:   WO2011057833-A1, US2011114919-A1, US8106383-B2, GB2487308-A, TW201126716-A, CN102612751-A, DE112010004367-T5, JP2013511139-W, GB2487308-B, DE112010004367-B4, CN102612751-B, JP5695656-B2, TW515896-B1
  • 发明人:   LIN Y, JENKINS K A, VALDES GARCIA A, VALDESGARCIA A, GARCIA A V, VALDES G A, LIN Y M
  • 专利权人:   INT BUSINESS MACHINES CORP, IBM UK LTD, INT BUSINESS MACHINES CORP, INT BUSINESS MACHINES CORP, INT BUSINESS MACHINES CORP, INT BUSINESS MACHINES CORP
  • 国际专利分类:   H01L029/786, H01L021/04, H01L029/16, H01L051/30, H01L021/336, H01L029/78, H01L021/28, H01L021/283, H01L021/316, H01L029/423, H01L029/49, H01L051/05
  • 专利详细信息:   WO2011057833-A1 19 May 2011 H01L-029/786 201135 Pages: 24 English
  • 申请详细信息:   WO2011057833-A1 WOEP062703 31 Aug 2010
  • 优先权号:   US617770

▎ 摘  要

NOVELTY - The graphene FET comprises a gate stack including a seed layer, a gate oxide formed over the seed layer and a gate metal formed over the gate oxide, an insulating layer (104), a graphene sheet displaced between the seed layer and the insulating layer, a spacer (602) formed on a top and both sides of the gate stack, and a source contact and a drain contact formed on the graphene sheet and separated from the gate stack by the spacer. The graphene sheet is deposited on the insulating layer, and is grown on the insulating layer. The seed layer comprises nitrogen dioxide. USE - Used as a graphene FET. ADVANTAGE - The self-aligned graphene FET is scalable, and has high carrier mobility, improved performance, reduced parastic capacitances, unique surface properties and increased transistor switching speed. DETAILED DESCRIPTION - The graphene FET comprises a gate stack including a seed layer, a gate oxide formed over the seed layer and a gate metal formed over the gate oxide, an insulating layer (104), a graphene sheet displaced between the seed layer and the insulating layer, a spacer (602) formed on a top and both sides of the gate stack, and a source contact and a drain contact formed on the graphene sheet and separated from the gate stack by the spacer. The graphene sheet is deposited on the insulating layer, and is grown on the insulating layer. The seed layer comprises nitrogen dioxide, a polymer and an oxidized metal film. The gate oxide is a high-k dielectric (502). The spacer has a portion removed to expose a portion of the gate metal. An INDEPENDENT CLAIM is included for a method of forming a graphene FET. DESCRIPTION OF DRAWING(S) - The diagram shows a schematic view of a structure of FET. Substrate (102) Insulating layer (104) Graphene layer (106) Gate electrode (402) Gate dielectric (502) Spacer (602) Electrodes. (802, 804, 806)