▎ 摘　　要

NOVELTY - The method involves forming an insulating buffer material layer on a dielectric layer and a set of gate lines (111). The insulating buffer material layer is patterned (113) to form a patterned insulating buffer layer comprising multiple separate portions, where each portion is extended to intersect the gate lines. A graphene layer is selectively grown (115) on the patterned insulating buffer layer. Another dielectric layer is formed (117) to cover the graphene layer and the formal dielectric layer. An upper gate electrode layer is formed (119) on the lateral dielectric layer. USE - Method for manufacturing a semiconductor device i.e. dual-gate graphene semiconductor device. ADVANTAGE - The method enables introducing ideal material into existing complementary metal-oxide-semiconductor (CMOS) manufacturing process so as to lower chip manufacturing costs while improving device performance. The method enables utilizing the selectively grown graphene to avoid undesired effects associated with patterning graphene using direct laser writing or photo-etching processes. The method enables reducing complexity of process steps of patterning the insulating buffer material layer for selective growth of graphene. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a flow diagram illustrating a method for manufacturing a semiconductor device. Step for forming insulating buffer material layer on dielectric layer and set of gate lines (111) Step for patterning insulating buffer material layer to form patterned insulating buffer layer (113) Step for selectively growing graphene layer on patterned insulating buffer layer (115) Step for another dielectric layer to cover graphene layer and formal dielectric layer (117) Step for forming upper gate electrode layer on lateral dielectric layer (119)