▎ 摘　　要

NOVELTY - The method involves using (S1) RDL process to prepare a first metal interconnection layer on the top metal of the metal oxide semiconductor (CMOS) measurement circuit system. A first dielectric layer is deposited (S2). A first sacrificial layer is deposited (S3) on the first dielectric layer. The through hole process and CMP planarization process are used (S4) to prepare the first interconnection pillar. A second metal interconnection layer is deposited (S5) on the first interconnection pillar. A second sacrificial layer is formed (S6). The through hole process and CMP planarization process are used (S7) to prepare a second interconnection pillar. A third metal interconnection layer and a second dielectric layer are deposited (S8), and the third metal interconnection layer is etched into a second patterned electrode structure to form an absorber plate. The second dielectric layer is thermal Sensitive medium layer. USE - Method of preparing multilayer structure infrared micro-bridge detector (claimed). ADVANTAGE - The problems of low performance, low pixel scale, low yield and poor consistency of a traditional MEMS process infrared micro-bridge detector are solved, and the performance of the infrared micro-bridge detector is optimized. The cost of the detector is reduced. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for an infrared micro-bridge detector. DESCRIPTION OF DRAWING(S) - The drawing shows a flowchart illustrating the method for preparing an infrared micro-bridge detector with a multilayer structure. (Drawing includes non-English language text) S1Step for using RDL process to prepare a first metal interconnection layer on the top metal of the CMOS measurement circuit system S2Step for depositing first dielectric layer S3Step for depositing first sacrificial layer S4Step for using through hole process and CMP planarization process to prepare the first interconnection pillar S5Step for depositing second metal interconnection layer S6Step for forming second sacrificial layer S7Step for using through hole process and CMP planarization process to prepare a second interconnection pillar S8Step for depositing third metal interconnection layer and a second dielectric layer