• 专利标题:   3D chip e.g. high power density power convertor, for consumer electronic devices, has super capacitors fabricated using graphene sheets, where intermediate levels comprise lateral heat transporters and vertical EMI shields.
  • 专利号:   IN201501355-I4
  • 发明人:   SHRIVASTAVA M
  • 专利权人:   INDIAN INST SCI
  • 国际专利分类:   H01L023/00
  • 专利详细信息:   IN201501355-I4 30 Sep 2016 H01L-023/00 201675 Pages: 27 English
  • 申请详细信息:   IN201501355-I4 INCH01355 19 Mar 2015
  • 优先权号:   INCH01355

▎ 摘  要

NOVELTY - The chip has a level-1 (302) comprising group III-Nitride based high electron mobility transistors and diodes placed over any or combination of Silicon, Silicon-Carbide and alumina substrate. A level-2 (304) comprises molybdenum disulphide based mixed signal IC. A level-3 (306) comprises super inductors fabricated using metallic Carbon Nanotubes. A level-4 (308) comprises super capacitors, where the super capacitors are fabricated using graphene sheets. Intermediate levels comprise lateral heat transporters and vertical EMI shields. USE - 3D chip e.g. high power density power convertor, high power density power inverter, high power RF trans-receiver and RF power amplifier (all claimed), for consumer power electronic devices. Uses include but are not limited to automobile industry, space industry, communication network, defense, railway and a machine tool industry. ADVANTAGE - The power electronic device is provided with significantly increased power density without sacrificing performance targets. The power electronic device is low in cost, size and weight. The power electronic device integrates HEMT on Silicon with molybdenum disulphide based controller chip and super inductors/capacitors. DETAILED DESCRIPTION - The lateral heat transporters are sandwiched between dielectric interlayers made of thermally conducting material. The level-4 uses a material selected from a group comprising dielectric material, graphene sheet, activated graphene, quantum nanocluster of metal oxides, graphite oxide and SWNT composite electrodes. The chip enables interconnects and vias fabricated using a high/super conducting material e.g. through- Silicon-Via (TSV), metallic Carbon Nanotubes and graphene. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view illustrating miniaturization of power electronics products by 3D integration of micro and nanotechnology. Level-1 comprising group III-Nitride based high electron mobility transistors and diodes (302) Level-2 comprising molybdenum disulphide based mixed signal IC (304) Level-3 comprising super inductors (306) Level-4 comprising super capacitors (308) Thermal conducting package (320)