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  • 专利标题:   Graphene wiring for semiconductor device comprises substrate, catalyst layer on substrate, graphene layer on catalyst layer, and dopant layer which contains atom or molecule in side surface of graphene layer.
  • 专利号:   JP5583236-B1, JP2014183210-A, US2014284800-A1, US9379060-B2
  • 发明人:   MIYAZAKI H, SAKAI T, KATAGIRI M, YAMAZAKI Y, SAKUMA H, SUZUKI M, SAKUMA N
  • 专利权人:   TOSHIBA KK, TOSHIBA KK, TOSHIBA KK
  • 国际专利分类:   C01B031/02, C23C016/26, H01B005/14, H01L021/28, H01L021/3205, H01L021/768, H01L023/532
  • 专利详细信息:   JP5583236-B1 03 Sep 2014 H01L-021/3205 201459 Pages: 9 Japanese
  • 申请详细信息:   JP5583236-B1 JP057004 19 Mar 2013
  • 优先权号:   JP057004

▎ 摘　　要

NOVELTY - A graphene wiring (10) comprises substrate, catalyst layer (12) on substrate, graphene layer (13) on catalyst layer, and dopant layer (14) which contains atom or molecule in side surface of graphene layer. Atom or molecule which migrates from dopant layer exists in interlayer of graphene layer or graphene layer. USE - A graphene wiring for semiconductor device. ADVANTAGE - The graphene wiring has low resistance. Scattering effect is prevented. DESCRIPTION OF DRAWING(S) - The drawing shows an isometric view of a semiconductor device with graphene wiring. Wiring (10) Catalyst base layer (11) Catalyst layer (12) Graphene layer (13) Dopant layer (14)