▎ 摘　　要

NOVELTY - The TFT (TR4) has a gate insulating layer (350) which is arranged between a gate electrode (GE3) and a semiconductor layer (340). A source electrode (SE3) is overlapped with the semiconductor layer. A drain electrode (DE3) is overlapped with the semiconductor layer, and spaced apart from the source electrode. A graphene pattern (330) is formed between the semiconductor layer and the source electrode or the drain electrode. A passivation layer arranged on the source electrode and the drain electrode is formed of silicon oxide and silicon nitride. USE - Thin film transistor (TFT) for use in display apparatus. ADVANTAGE - The graphene pattern is formed between the drain electrode and the gate insulating layer, so that the productivity and the reliability of the TFT can be improved. Since the passivation layer is not lifted off from the source electrode and the drain electrode due to the second graphene pattern, there is no need of etch stopper for protecting the oxide semiconductor. Thus, the process of manufacturing the TFT can be simplified and the manufacturing cost of the TFT can be decreased. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for manufacturing a TFT. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of the array substrate. Graphene pattern (330) Semiconductor layer (340) Gate insulating layer (350) Drain electrode (DE3) Gate electrode (GE3) Source electrode (SE3) TFT (TR4)