• 专利标题:   Graphene metal oxide semiconductor (MOS) transistor for graphene-based integrated circuit, has gate region arranged on trench region while gate medium is arranged between gate region and trench region.
  • 专利号:   CN101783366-A
  • 发明人:   WANG P, ZHANG W, LIU H, GU J
  • 专利权人:   UNIV FUDAN
  • 国际专利分类:   H01L021/324, H01L021/336, H01L029/16, H01L029/78
  • 专利详细信息:   CN101783366-A 21 Jul 2010 H01L-029/78 201057 Pages: 11 Chinese
  • 申请详细信息:   CN101783366-A CN10111271 11 Feb 2010
  • 优先权号:   CN10111271

▎ 摘  要

NOVELTY - The graphene MOS transistor has semiconductor substrate such as monocrystalline silicon, polysilicon or silicon-on-insulator, which has gate region, source region, a drain region and trench region. The gate region and the trench region are positioned between source region and drain region. The gate region is arranged on the trench region while a gate medium is arranged between gate region and trench region. USE - Graphene metal oxide semiconductor (MOS) transistor for graphene-based integrated circuit. ADVANTAGE - The gate leakage current of the graphene MOS transistor can be reduced. The contact resistance between source/drain and trench can be reduced. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for manufacturing method of graphene (MOS) transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the graphene MOS transistor.