• 专利标题:   Semiconductor device, for use in variety of electronic applications, such as personal computers, cellular telephones, digital cameras, comprises substrate, first pad positioned above substrate, and first redistribution structure comprising first redistribution conductive layer positioned first pad.
  • 专利号:   US2022165639-A1, CN114520207-A, US11495516-B2, TW202234618-A, TW786754-B1
  • 发明人:   HO J, HE J
  • 专利权人:   NANYA TECHNOLOGY CORP, NANYA TECHNOLOGY CORP, NANYA TECHNOLOGY CORP, NANYA TECHNOLOGY CORP
  • 国际专利分类:   H01L021/02, H01L023/00, H01L023/373, H01L021/60, H01L023/367, H01L023/488, H01L021/56
  • 专利详细信息:   US2022165639-A1 26 May 2022 H01L-023/373 202250 English
  • 申请详细信息:   US2022165639-A1 US100330 20 Nov 2020
  • 优先权号:   US100330

▎ 摘  要

NOVELTY - Semiconductor device comprises a substrate (101, a first pad positioned above the substrate, and a first redistribution structure comprising a first redistribution conductive layer positioned on the first pad and a first redistribution thermal release layer positioned on the first redistribution conductive layer, where the first redistribution thermal release layer is configured to sustain a thermal resistance between 0.04-0.25 degreesC cm2/Watt. USE - Semiconductor device (claimed), for use in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment ADVANTAGE - The device has improved quality, yield, performance, reliability, and reduced complexity. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for method for fabricating a semiconductor device, which involves providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer, where the first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between 0.04-0.25 degreesC cm2/Watt. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart of the method. Substrate (101) Interconnection layer (103) Device elements (105) First conductive pattern (107) Bottom passivation layer (111)