▎ 摘　　要

NOVELTY - The self-aligned narrow bandgap semiconductor device with high on-off ratio, has a narrow bandgap semiconductor layer (103) and a metal gate stack structure (105) on a supporting substrate (101). The gate stack has sidewalls (108, 108') formed by a self-aligned process and having an L-shape at two sides, and respectively defining a source region and a drain region outside the sidewalls. A gate dielectric layer (104) is arranged between the gate stack structure and the narrow bandgap semiconductor layer. The side walls have an L-shaped profile formed by a vertical portion and a horizontal portion. The horizontal portion and the gate dielectric layer located below it respectively extend to a certain length along the source region and the drain region which are outside the plane of the narrow bandgap semiconductor layer. The horizontal part and the narrow bandgap semiconductor layer are covered with a metal layer to form a source electrode (110) and a drain electrode. USE - Narrow band gap semiconductor device i.e. carbon nano-tube field-effect transistor. ADVANTAGE - The semiconductor transistor structure is very simple and efficient. The problem of static power consumption caused by off-state tunneling current can be effectively solved without using any traditional ion implantation or doping process or adopting a complex multilayer film structure or various work function adjusting steps and processes. The problem of device bipolarity caused by narrow-band gap of the material is effectively inhibited. The on-off ratio of the narrow-band gap semiconductor transistor is improved. The processing method of the semiconductor transistor structure is compatible with the general silicon-based integrated circuit manufacturing process. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a manufacturing method of the self-aligned narrow bandgap semiconductor device with high switching ratio. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram of the structure after interlayaer dielectric layer chemical mechanical polishing planarization. a schematic diagram of the structure after ILD dielectric layer CMP planarization; Supporting substrate (101) Narrow bandgap semiconductor layer (102) Narrow bandgap semiconductor layer (103) Gate dielectric layer (104) Metal gate stack structure (105) Sidewalls (108, 108') Source electrode (110) Etching stop layer (111) Interlayer dielectric layer (112)