▎ 摘　　要

NOVELTY - Manufacturing memory device (20) involves forming first redistribution patterns (449B) in a first dielectric layer; forming second redistribution patterns electrically connected with the first redistribution patterns on the first dielectric layer with a first material; forming a thermally conductive layer electrically isolated from the first redistribution patterns and the second redistribution patterns over the first dielectric layer with a second material different form the first material; and forming a second dielectric layer over the first dielectric layer, where the second redistribution patterns and the thermally conductive layer are embedded in the second dielectric layer. USE - The method is useful for manufacturing memory device (claimed). ADVANTAGE - The structures and methods may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for: (1) a method which involves forming a memory cube to include multiple stacked tiers (10A-10D), where each tier of the multiple stacked tiers is formed to include: first semiconductor dies (110, 210, 310, 410, 510) laterally wrapped by an encapsulant (130, 230, 330, 430); and a redistribution structure (140, 240, 340, 440) disposed on the first semiconductor dies and the encapsulant, where each redistribution structure in the multiple stacked tiers includes redistribution patterns; and mounting the memory cube on a second semiconductor die, where the first semiconductor dies of the multiple stacked tiers are electrically connected with the second semiconductor die through the redistribution structures in the multiple stacked tiers, the redistribution structure closest to the second semiconductor die further includes a thermally conductive layer connected to the second semiconductor die, a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the second semiconductor die, and the thermally conductive layer is electrically isolated from the first semiconductor dies in the multiple stacked tiers and the second semiconductor die; and (2) a method which involves providing a logic die; forming a memory cube to include a first tier, at least one second tier, and a third tier, where the at least one second tier is located between the first tier and the third tier, the first tier is closest to the logic die, and each of the first tier, the at least one second tier and the third tier is formed by: providing semiconductor dies; encapsulating the semiconductor dies in an encapsulating; and forming a redistribution structure on the semiconductor dies and the encapsulant, where the redistribution structure of the first tier includes a thermally conductive layer, the thermally conductive layer of the first tier extends laterally beyond spans of the semiconductor dies in the first tier, and the thermally conductive layer of the first tier is electrically isolated from the semiconductor dies of the memory cube and the logic die; forming connectors (450) on and connected with the redistribution structure of the first tier; mounting the memory cube on the logic die through the connectors; and forming a molding compound (530) laterally wrapping the memory cube and wrapping around the connectors. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic cross-sectional vies of structure produced at various stages of a manufacturing method of a memory device. Tiers (10A-10D) Memory device (20) Encapsulants (130, 230, 330, 430) Redistribution structures (140, 240, 340, 440 ) Redistribution pattern (449B)