• 专利标题:   Transistor useful for electronic devices such as a radio frequency device for high frequency and display, comprises a channel layer including graphene, a gate insulating layer, a gate facing the channel layer, and a source and a drain.
  • 专利号:   US2014021446-A1, EP2690664-A1, KR2014013405-A, CN103579310-A, US9040958-B2, EP2690664-B1, CN103579310-B, KR1919424-B1
  • 发明人:   LEE C, KIM Y, LEE J, JUNG Y, LEE C S, KIM Y S, LEE J H, JUNG Y S
  • 专利权人:   SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO LTD
  • 国际专利分类:   H01L029/16, H01L029/66, H01L029/78, H01L029/49, H01L029/786, H01L021/336, H01L021/335, H01L029/06
  • 专利详细信息:   US2014021446-A1 23 Jan 2014 H01L-029/16 201410 Pages: 30 English
  • 申请详细信息:   US2014021446-A1 US792525 11 Mar 2013
  • 优先权号:   KR080251

▎ 摘  要

NOVELTY - Transistor comprises: a channel layer (C10) including graphene; a gate insulating layer (GI10) on a surface of the channel layer; a gate facing the channel layer; and a source and a drain electrically connected to first and second regions of the channel layer, respectively. The gate insulating layer includes fluorinated graphene. The gate insulating layer is in between the gate and the channel layer. USE - The transistor is useful for various electronic devices such as a radio frequency device for high frequency and display. ADVANTAGE - The transistor: prevents interface defects between a graphene channel layer and a material layer (e.g. a gate insulating layer) which contacts the graphene channel layer; and is manufactured easily without etching process, with improved productivity, reduced cost and high quality. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for: (1) a method (m1) of manufacturing a transistor, comprising (a) forming a multilayer structure including a channel layer having graphene and a gate insulating layer including fluorinated graphene, (b) forming a gate facing the channel layer, where the gate insulating layer is interposed between the gate and the channel layer, and (c) forming the source and the drain; and (2) a method (m2) of manufacturing a transistor, comprising (a1) preparing a multilayer structure including a channel layer and a gate insulating layer on the channel layer, where the channel layer includes a patterned graphene region defined by a region chemically converted from graphene, and steps (b) and (c) as above per se. DESCRIPTION OF DRAWING(S) - The figure shows a cross-sectional view of the transistor. Channel layer (C10) Gate electrode (G10) Gate insulating layer (GI10) Substrate (SUB10) Underlayer (UL10)