▎ 摘　　要

NOVELTY - The semiconductor device has a substrate comprising an element isolation layer defining an active region (ACT). Multiple word lines (WL) traverse the active region in a first direction. Multiple bit line (BL) structures are set on the substrate, and connected to the active region. Multiple bit line structures are extended in a second direction different from the first direction. Multiple bit line structures include a ruthenium wiring having a bottom surface and a top surface opposite to the bottom surface. A lower graphene layer is in contact with the lower surface of the ruthenium wiring, and extends along the lower surface of the ruthenium wiring and a wiring line cap layer extends along the upper surface of the ruthenium wiring. USE - Semiconductor device e.g. dynamic random access memory (DRAM). ADVANTAGE - The performance of the semiconductor device can be improved, by using a material with a low specific resistance and/or a high mean free path of electrons for the wiring. The lower graphene layer can reduce the resistance of the first line wiring. The lower graphene layer improves current distribution between the wiring structure and the bit line contact. The speed of the semiconductor device can be increased with a reduction in contact resistance. The contact resistance between the active region ACT and the bottom electrode of the capacitor can be reduced, by expanding the contact area through the insertion of the second landing pad. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram illustrating the semiconductor device. Active region (ACT) Bit line (BL) Buried contacts (BC) Digit line contact (DC) Word lines (WL)