▎ 摘　　要

NOVELTY - The method involves forming a layer of graphene over a substrate (102). An insulating layer (104) is formed over substrate. FET is provided with a top gate orientation relationship based on the associated graphene layer. The top gate orientation FET is formed by patterning the associated graphene layer based on a desired active layout area. A gate dielectric layer and a gate electrode layer are formed over the patterned graphene layer. The portions of the gate dielectric layer and gate electrode layer are removed in accordance with a desired gate pattern. USE - Method of forming three-dimensional (3D) integrated circuit (IC) structure used in semiconductor industry. ADVANTAGE - The gate dielectric layer and the gate electrode layer are formed over the patterned graphene layer, so that the signal propagation delay can be reduced. Hence the overall performance of the IC structure can be enhanced. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of the IC structure. Substrate (102) Insulating layer (104) Lower level of graphene (124) Upper level of graphene (126)