▎ 摘　　要

NOVELTY - The semiconductor device has catalyst layer (22) formed on or in substrate (10) along with interconnect pattern, and graphene layers (23) formed on catalyst layer. The graphene layers are arranged in parallel in a narrower line width than a width of interconnect pattern. The catalyst layer is embedded in groove arranged in interconnect layer insulating film (13) in uppermost layer of substrate. USE - Semiconductor device using graphene for interconnecting large-scale integration (LSI). ADVANTAGE - Graphene can be used as an interconnect having ultimately low resistance instead of a metallic interconnect and is advantageous with respect to electrical conduction in a long-distance interconnect, since graphene exhibits quantized conduction properties. Allows chemical elements to be easily introduced to each of the separated graphene layers, which further reduces resistance of the graphene layer, thus, it is possible to reduce interconnect resistance and contribute to improving the performance of a semiconductor device. It is possible to finely separate and form the graphene layer in a wide-width interconnect layer and to reduce interconnect resistance. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method of manufacturing a semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view illustrating a process of manufacturing semiconductor device. Substrate (10) Interconnect layer insulating film (13) Catalyst underlayer (21) Catalyst layer (22) Graphene layers (23)