• 专利标题:   System on chip (SOC) architecture design system has multiple processors that are in built with other blocks of memory and control logic developed by nonmaterial.
  • 专利号:   IN202241048824-A
  • 发明人:   NARMADHA R, NISHA S A A, BALAMURUGAN V, VEDANARAYANAN V
  • 专利权人:   NARMADHA R, NISHA S A A, BALAMURUGAN V, VEDANARAYANAN V
  • 国际专利分类:   G06F001/16, G06F001/3234, G06F013/40, G06F015/78, H04L029/08
  • 专利详细信息:   IN202241048824-A 02 Sep 2022 G06F-015/78 202298 Pages: 14 English
  • 申请详细信息:   IN202241048824-A IN41048824 26 Aug 2022
  • 优先权号:   IN41048824

▎ 摘  要

NOVELTY - The system has multiple processors that are in built with other blocks of memory and control logic developed by nonmaterial. A smart controller exchanges data between various processors and in-unit output devices. A controller block controls the data flow between memory and different SoC components and processors. A memory access controller (MAC) manages and accelerates data transmission speed, and reduces the processor's activity for SoC based devices. The graphene-based on-chip antenna array empowers energy efficient, multi-modal inter-chip communication protocol for multichip systems. The antenna reduces the radiation effect, and reduces power consumption in SOC. USE - System on chip (SOC) architecture design system for use in mobile phones, set-top boxes, wearables, automobiles, medical equipment, point-of-sale terminals, internet of things (IoT) gateways, networking equipment and artificial intelligence platforms. ADVANTAGE - The architecture is modular, efficient, scalable, reliable, simple, and it is able to support high application demands. The security layer also prevents and anticipates the dangers and cyber-attacks, including the forensics to detect the type of attack and fail them. The SoC designs can implement high-performance and inexpensive systems for many killer applications with greater device integration. The overall system performance, flexibility, and scalability, power/thermal management, system partition (among digital, analog, on-chip, or off-chip), architecture partition (between hardware and software), algorithm developments fore merging applications, and so on. DESCRIPTION OF DRAWING(S) - The drawing shows a block diagram of the IOT architecture.