• 专利标题:   Manufacture of graphene flash memory involves patterning conductive layer formed on semiconductor substrate, forming source/drain electrodes, dielectric layers, graphene layer and gate electrode, and etching dielectric layers.
  • 专利号:   CN104192835-A, CN104192835-B
  • 发明人:   WANG H, JIANG M, LI L, XIE X, WU T, CHEN J, LU G, XIE H, ZHANG X
  • 专利权人:   SHANGHAI INST MICROSYSTEM INFORMATION, SHANGHAI INST MICROSYSTEM INFORMATION
  • 国际专利分类:   C01B031/04, H01L021/336
  • 专利详细信息:   CN104192835-A 10 Dec 2014 C01B-031/04 201518 Pages: 16 Chinese
  • 申请详细信息:   CN104192835-A CN10466181 12 Sep 2014
  • 优先权号:   CN10466181

▎ 摘  要

NOVELTY - Manufacture of graphene flash memory involves forming conductive layer on semiconductor substrate, patterning conductive layer to form strip, forming source/drain contact electrodes, forming dielectric layer (a) on drain contact electrode, exposing the substrate, forming a graphene layer on the dielectric layer (a), patterning graphene layer to form a strip, forming dielectric layer (b) between graphene layer and dielectric layer (b), forming gate electrode on dielectric layer (b), and etching the dielectric layers (a) and (b) to expose the source/drain contact electrodes. USE - Manufacture of graphene flash memory (claimed). ADVANTAGE - The method enables simple and efficient manufacture of graphene flash memory with reduced power consumption during rapid writing, erasing and reading function. DETAILED DESCRIPTION - Manufacture of graphene flash memory involves providing a semiconductor substrate, forming a conductive layer on the semiconductor substrate, patterning the conductive layer to form a strip, forming source electrode and drain contact electrode at both ends of the conductive layer, forming dielectric layer (a) on drain contact electrode, exposing the semiconductor substrate, forming a graphene layer on the dielectric layer (a), patterning graphene layer to form a strip, providing the graphene layer between the source electrode and the drain contact electrode, forming dielectric layer (b) between graphene layer and dielectric layer (b), forming gate electrode on dielectric layer (b), and etching the dielectric layers (a) and (b) to expose the source/drain contact electrodes.