▎ 摘　　要

NOVELTY - The FET has a bottom gate medium layer (2) located in a bottom gate electrode (1) that is arranged above a double-layer graphene active area (5). The bottom gate medium layer is arranged above a metal source electrode (6). A drain electrode metal (7) is provided in the double-layer graphene active area. The double-layer graphene active area, the metal source electrode and drain electrode metal are made of different materials. A top gate electrode (9) is located in a top gate medium layer (8). USE - Double-layer graphene tunneling FET. ADVANTAGE - The FET has simple preparation process and better tunneling effect. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a double-layer graphene tunneling FET preparation method. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a double-layer graphene tunneling FET. Bottom gate electrode (1) Bottom gate medium layer (2) Double-layer graphene active area (5) Metal source electrode (6) Drain electrode metal (7) Top gate medium layer (8) Top gate electrode (9)