• 专利标题:   Fabrication method for semiconductor devices, involves depositing layer of material by self-aligning deposition process, to form source and drain, and removing layer of graphene from gate and from portion of dielectric layer.
  • 专利号:   US10153159-B1
  • 发明人:   KIM S, LEE Y S, SADANA D, DE SOUZA J
  • 专利权人:   INT BUSINESS MACHINES CORP
  • 国际专利分类:   H01L021/02, H01L021/306, H01L029/08, H01L029/20, H01L029/227, H01L029/267, H01L029/66, H01L029/78
  • 专利详细信息:   US10153159-B1 11 Dec 2018 H01L-021/02 201901 Pages: 13 English
  • 申请详细信息:   US10153159-B1 US827108 30 Nov 2017
  • 优先权号:   US827108

▎ 摘  要

NOVELTY - The fabrication method involves transferring a layer of graphene (130) to a surface of a dielectric layer (110) on a semiconductor substrate (100) and a gate (120) formed on the dielectric layer. A portion of the layer of graphene on the dielectric layer is removed, in which the removed portion is not adjacent to the gate. A portion of the dielectric layer is removed and a top portion of the semiconductor substrate not covered by the portion of the layer of graphene remaining is partially removed. A layer of a material is deposited by a self-aligning deposition process, in which the layer of the material creates a source and a drain in a semiconductor device. The layer of graphene is removed from the gate and from a portion of the dielectric layer remaining adjacent to the gate. USE - Fabrication method for semiconductor devices, such as MOSFET devices. ADVANTAGE - The fabrication method provides self-aligned processes associated with the source and drain material deposition which enables reliable device manufacturing processes in nanometer-scale semiconductor devices. The undercut of semiconductor substrate provides an ability to overlap an area of the source and drain with a gate controlled area of semiconductor substrate for improved electrical performance of the semiconductor device. DESCRIPTION OF DRAWING(S) - The drawings show the cross-sectional views of the semiconductor substrate after depositing a layer of graphene and after etching a portion of the graphene layer, a portion of the dielectric layer and a portion of the semiconductor layer. Semiconductor substrate (100) Dielectric layer (110) Gate (120) Layer of graphene (130)