▎ 摘　　要

NOVELTY - The semiconductor structure has a first conductive feature which is embedded within a first dielectric layer. A via is arranged over the first conductive feature. A second conductive feature is arrangedover the via. The via electrically couples the first conductive feature to the second conductive feature. A graphene layer (220) is arranged over a portion of the first conductive feature. A third conductive feature is embedded within the first dielectric layer. A top surface of the third conductive feature is co-planar with a top surface of the first conductive feature. An amorphous carbon layer is formed. USE - Semiconductor structure for manufacturing integrated circuit (IC) device (claimed). ADVANTAGE - The risk of forming a short circuit between the via and a neighboring conductive feature is minimized in the event of misalignment. The presence of the graphene layer reduces the contact resistance between the metal capping layer with formed conductive features over the graphene layer. The short circuit concern due to the close spacing between the conductive features are eliminated even in case of misalignments. The device reliability and performance are improved. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method of manufacturing integrated circuit (IC) device. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of the interconnect structure of the semiconductor device at various stages of fabrication. Semiconductor device (200 ) Substrate (206) Inter-level dielectric (210) Conductive features (212, 214) Graphene layer (220)