• 专利标题:   Integrated circuit preparation method, involves growing up silicon wafer of sulfur dioxide by utilizing evaporation process, and exposing hexagonal boron nitride layer on surface of graphene containing layer by metal evaporation process.
  • 专利号:   CN103633024-A, CN103633024-B
  • 发明人:   ZHANG P, MA Z, WU Y, ZHUANG Y, FENG Y, ZHAO Y, CHEN Y
  • 专利权人:   UNIV XIDIAN
  • 国际专利分类:   B82Y010/00, H01L021/336, H01L021/82
  • 专利详细信息:   CN103633024-A 12 Mar 2014 H01L-021/82 201429 Chinese
  • 申请详细信息:   CN103633024-A CN10562335 11 Nov 2013
  • 优先权号:   CN10562335

▎ 摘  要

NOVELTY - The method involves growing up silicon wafer of sulfur dioxide by utilizing evaporation process and growing a primary catalytic metal layer. A secondary catalyzing mental layer is obtained by utilizing the photo etching process. A hexagonal boron nitride layer is grown up on the secondary catalytic metal layer by utilizing CVD method. The hexagonal boron nitride layer is exposed on the surface of the graphene containing layer by utilizing metal evaporation process. USE - Integrated circuit preparation method. ADVANTAGE - The method enables providing simple preparation process with low rate of finished products. DESCRIPTION OF DRAWING(S) - The drawing shows a side view of an integrated circuit. '(Drawing includes non-English language text)'