▎ 摘　　要

NOVELTY - The device has a catalyst underlying layer (13) formed on a semiconductor substrate (10) including semiconductor elements. The catalyst underlying layer is processed in a wiring pattern. A catalyst metal layer (14) is formed on the catalyst underlying layer. The catalyst metal layer includes width narrower than width (L) of the catalyst underlying layer. A roll form graphene layer (15) is formed to surround the catalyst metal layer, and grows with a side surface of the catalyst metal layer to set as a growth origin, where a facet is formed on the side surface of the catalyst metal layer. USE - Semiconductor device. ADVANTAGE - The graphene layer is formed in roll form such that a number of hexagonal lattice structures of graphene sheets can be increased without being restricted by wire width, so that influence by edge scattering effect on resistance of a graphene end portion can be reduced, and a graphene wiring structure exhibiting low resistance even with minute wire width can be realized. The graphene layer is uniformly formed around the catalyst metal layer and continued along current flow direction, so that an electron path is formed along the current flow direction, and a low-resistance wiring structure is realized. DETAILED DESCRIPTION - The catalyst underlying layer is an underlying metal film. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a semiconductor device. Width of catalyst underlying layer (L) Semiconductor substrate (10) Catalyst underlying layer (13) Catalyst metal layer (14) Roll form graphene layer (15)