▎ 摘　　要

NOVELTY - The transistor (100) has a graphene layer (40) formed on a gate insulating film (30). First transition metal dichalcogenide (TMDC) pattern (51) and second TMDC pattern (52) are formed to cross the graphene layer in transverse direction and spaced at predetermined distance in longitudinal direction of the graphene layer. A control unit controls direction of spin of electrons generated between the graphene layer and the first TMDC pattern, where voltage difference between a point (61) of the second TMDC pattern and a point (62) of the graphene layer adjacent to the second TMDC pattern in opposite direction of the first TMDC pattern is zero in transistor off state and non-zero in transistor on state. USE - Graphene spin transistor i.e. FET, for use in non-memory or memory semiconductor based electrical and electronic applications, unmanned vehicles, and internet of things devices. ADVANTAGE - The transistor utilizes Rashba Edelstein effects of graphene and spin hole effects of TMDC patterns so as to electrically operate the transistor at room temperature without forming a magnetic field, thus reducing power consumption and cost of the transistor, and effectively commercializing the transistor. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for manufacturing a Graphene spin transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a perspective view of a graphene spin transistor. Gate insulating film (30) Graphene layer (40) TMDC patterns (51,52) TMDC pattern points (61,71) Graphene layer points (62,72) Graphene spin transistor (100)