• 专利标题:   Preparation method for two-dimensional floating gate photoelectric transistor, involves stacking single-layer charge graphene trapping layer/tunneling layer/two-dimensional transition metal sulfide channel layer.
  • 专利号:   CN115332079-A
  • 发明人:   HAN G, LIU Y, ZHANG S, YANG Q, LUO Z
  • 专利权人:   UNIV XIDIAN
  • 国际专利分类:   H01L021/336, H01L027/11517, H01L027/11521, H01L029/788
  • 专利详细信息:   CN115332079-A 11 Nov 2022 H01L-021/336 202316 Chinese
  • 申请详细信息:   CN115332079-A CN10959972 11 Aug 2022
  • 优先权号:   CN10959972

▎ 摘  要

NOVELTY - Preparing two-dimensional floating gate photoelectric transistor comprises (i) sequentially distributing two-dimensional semiconductor channel layers (5) on a back-gate substrate (1), an oxide layer (2), a charge-trapping layer (3), a tunneling layer (4), a semiconductor transition metal sulfide material, a source (6) and a drain (7), (ii) a charge trapping layer, (3) a single-layer material graphene graphene, (4) a tunnel layer, a two-dimensional hexagonal boron nitride material, (5-5) using the two-dimensional semiconductor conversion metal sulfide material to sequentially distribute the two semiconducting channel layers from bottom to top on the back gate substrate, and (6-7) the source and the drain are respectively located at both ends of the two dimensional semiconductor circuit layer. USE - Preparation method for two-dimensional floating gate photoelectric transistor used for calculating in reconfigurable logic calculation and visual information sensor used in machine vision system. ADVANTAGE - The charge-trapping layer uses a single-layer material graphene to realize positive and negative photoconductive switch in the same device, compared with the existing only can realize positive photoelectric response of the device has a higher degree of freedom of operation, and it also realizes the reconfigurable logic calculation and photoelectric synaptic simulation of and/or non-reconfigurable non-volatile photoelectric logic under different photoelectric pulse input. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram of the preparation method for two-dimensional floating gate photoelectric transistor. 1Back-gate substrate 2Oxide layer 3Charge trapping layer 4Tunnelling layer 5Two-dimensional semiconductor channel layer 6Source 7Drain