▎ 摘　　要

NOVELTY - Enhanced switch transistor based on array strip comprises substrate (1), transition layer (2) and barrier layer (3). The upper portion of barrier layer is provided with P-gallium nitride (P-GaN) gate (4). The upper portion of P-GaN gate is deposited with gate metal (8). The upper portion of left and right side edge of barrier layer is respectively provided with source electrode (6) and drain electrode (7), where barrier layer between P-GaN grid and the drain electrode is provided with modulation electrode (5). The modulation electrode is composed of array strip at the lower portion and strip metal at the upper portion. The array strip is composed of isolation strips with equal distance. The isolation strips are horizontally placed and arranged in parallel on barrier layer. The doping concentration of each isolation strip is 5x1015-1x1022 cubic centimeter (cm-3). USE - Enhanced switch transistor based on array strip used in the field of micro-elecronics as basic device of power electronic system, and used in the national economy and military fields. ADVANTAGE - The device uses modulation electrode electrically connected with drain electrode, which modulates p-n junction with barrier layer when device switch is working, effectively inhibits charging and discharging of device surface and in the body defect, which inhibits current collapse phenomenon, at the same time, as the array strip and P-GaN gate are made of same layer of P-type gallium nitride layer material, which simplifies the manufacturing process. The modulation electrode used by the device is composed of isolation strips and strip metal on upper portion, and has good frequency characteristic because parasitic capacitance of device is hardly increased while ensuring good output characteristics of device as compared with other methods such as a field plate structure. The device has good reliability and output power characteristics, manufacturing yield of device is improved, and manufacturing cost of device is reduced. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for manufacturing enhanced switch transistor based on an array strip, which involves: (a) growing GaN based wideband gap semiconductor material epitaxially on a substrate to form transition layer; (b) extending GaN based wide bandgap semiconductor material on transition layer to form barrier layer with thickness of a; (c) forming P-type GaN semiconductor material epitaxially on barrier layer with thickness of b' and doping concentration of 5x1015-1x1022 cm-3; (d) manufacturing mask on P-type GaN layer for first time, etching P-type GaN layer by using mask until upper surface of barrier layer is etched to form P-GaN gate with thickness of b on left side and P-GaN blocks which are arranged in parallel and are equidistant and with thickness of b' on right side, where distance between every two adjacent P-GaN blocks is w'; (e) manufacturing mask on barrier layer, P-GaN gate and P-GaN blocks for the second time, etching P-GaN blocks by using mask, where etching depth f is greater than or equal to 0 microns and smaller than thickness of P-GaN gate, and forming equally-spaced isolating strips with thickness of c' on right side, almost no depletion effect of each isolating strip on two-dimensional electron gas in channel formed between lower barrier layer and transition layer of device is realized in a balanced state when c' is less than or equal to 5 nanometer (nm), and depletion effect of each isolating strip on two-dimensional electron gas in channel formed between lower barrier layer and transition layer of device is gradually increased along with the increase of thickness c' of each isolating strip when c' is greater than 5 nm, distance between first isolating bar and upper boundary of device is equal to distance between the isolating bar and lower boundary of device; (f) manufacturing mask on barrier layer, P-GaN gate and array strip for third time, depositing metal on upper portions of barrier layer on left side and right side by using mask, and performing rapid thermal annealing to finish manufacture of source electrode and drain electrode, where horizontal distance between left end of drain electrode and right end of array strip is more than or equal to 0 microns; (g) making mask on barrier layer, P-GaN gate, array strip, source electrode and drain electrode for fourth time, and depositing metal on upper portion of P-GaN gate by using mask to finish making of gate metal; and (h) making mask on barrier layer, P-GaN gate, array strips, source electrode, drain electrode and gate metal for fifth time, depositing metal on upper portion of each isolation strip in array strips by using mask to form strip metal, and connecting strip metal electrically with drain electrode to finish the manufacture of whole device. DESCRIPTION OF DRAWING(S) - The drawing shows schematic view of enhanced switch transistor based on array strip. (Drawing includes non-English language text). Substrate (1) Transition layer (2) Barrier layer (3) P-gallium nitride gate (4) Modulation electrode (5) Source electrode (6) Drain electrode (7) Gate metal (8)