▎ 摘　　要

NOVELTY - Manufacturing a field effect transistor (FET) involves (1) forming a gate electrode, a gate dielectric layer, and a channel layer on a substrate, where the channel layer is made of a two-dimensional (2D) material, (2) forming an insulating layer, an etching stop layer, and a protective layer on the channel layer, (3) etching the insulating layer, the etching stop layer, and the protective layer to form two through holes, the two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer; (4) performing a plasma treatment on the channel layer, and (5) forming a source electrode and a drain electrode, where the source electrode and the drain electrode are respectively in a corresponding one of the two through holes and form a top contact with the channel layer. USE - Method for manufacturing a field effect transistor (FET) used in 2D material as the channel layer. ADVANTAGE - The FET has high electron mobility and avoids short-channel effects, has electrically connected to the peripheral circuit, which has improved the stability of the integrated circuit. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for: (1) a field effect transistor (FET), which comprises a substrate, a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, where the channel layer is made of a two-dimensional (2D) material, an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, where the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer, and a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer; and (2) an integrated circuit, which comprises a peripheral circuit and at least one FET electrically connected to the peripheral circuit, at least one FET comprising a substrate, a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, where the channel layer is made of a two-dimensional (2D) material, an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, where the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer, and a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer.