▎ 摘　　要

NOVELTY - The FET has a semiconductor-on-insulator type substrate provided from a base towards a surface. A single ferroelectric layer (2) is arranged in direct contact with a semiconductor support substrate (1) and biased to form a negative capacitance. An active layer (3a) of a semiconductor material is adapted to form a channel of the transistor and arranged in direct contact with the ferroelectric layer. A channel (3b) is arranged in the active layer. A source (11) and a drain are arranged in the active layer. A gate is arranged on the channel and insulated from the channel by a gate dielectric. The support substrate is formed of silicon, germanium, silicon-germanium alloy, gallium arsenide, indium phosphide, gallium-indium arsenide, graphene or tungsten disulfide. USE - Negative-capacitance FET for use in a microelectronic field. ADVANTAGE - The FET allows better control of electric current in the active layer, faster switching of the transistor, and improved coupling with the gate on the rear face. The FET has a simple structure, and can be manufactured with existing processes. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for manufacturing a negative-capacitance FET. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a negative-capacitance FET. 1Semiconductor support substrate 2Single ferroelectric layer 3aActive layer 3bChannel 11Source