• 专利标题:   Transistor has substrate layer formed with concave part, concave part has bottom surface, where lower surface of semiconductor channel region and bottom surface of concave part have a preset distance, or part of semiconductor channel region and bottom surface of concave part are contact.
  • 专利号:   CN114824086-A
  • 发明人:   ZHANG Z, CAO Y, LIN Y
  • 专利权人:   BEIJING HUATANYUANXIN ELECTRONIC TECHNOL, BEIJING YUANXIN CARBONBASED INTEGRATED, UNIV PEKING
  • 国际专利分类:   H01L051/05, H01L051/30, H01L051/40
  • 专利详细信息:   CN114824086-A 29 Jul 2022 H01L-051/05 202277 Chinese
  • 申请详细信息:   CN114824086-A CN10447049 26 Apr 2022
  • 优先权号:   CN10447049

▎ 摘  要

NOVELTY - The transistor has a semiconductor channel region formed above the substrate layer. A first electrode and second electrode are formed in the semiconductor channel region. A preset distance interval is between first electrode and second electrode. A gate dielectric layer is formed on at least a part of the upper surface of the semiconductor channel region. The substrate layer is formed with a concave part. The concave part has a bottom surface. The lower surface of semiconductor channel region and bottom surface of concave part have a preset distance, or the part of semiconductor channel region and bottom surface of concave part are contact. The materials for forming semiconductor channel region comprise semiconductor metal oxides, two-dimensional transition metal sulfides, graphene, carbon nano-tube, carbon nano-wire, semiconductor nano-wire, organic semiconductors, black phosphorus or molybdenum disulfide. USE - Used as transistor. ADVANTAGE - The transistor: prevents the recess from being formed on lower end of gate dielectric layer so as to prevent short-circuit between recess and gate electrode, diffusion of impurities e.g. impurities from the substrate layer into channel regions of transistor, and the transistor from being damaged by the impurities; and improves reliability and performance of transistors. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a preparation method of transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a structure schematic diagram of the transistor.