• 专利标题:   Ternary logic device has first transistor and second transistor that are connected in parallel to form ternary logic element that implements logic state, and heterojunction-based multilayer channel is formed by sequentially stacking lower semiconductor material layer.
  • 专利号:   KR2022014629-A, KR2370741-B1
  • 发明人:   LEE K Y, JANG H, LEE D G, LEE B H
  • 专利权人:   GWANGJU INST SCI TECHNOLOGY
  • 国际专利分类:   H01L027/088, H01L029/16, H01L029/786
  • 专利详细信息:   KR2022014629-A 07 Feb 2022 H01L-029/786 202217 Pages: 21
  • 申请详细信息:   KR2022014629-A KR094471 29 Jul 2020
  • 优先权号:   KR094471

▎ 摘  要

NOVELTY - The device has a channel layer (140) positioned on a substrate (110), and a source electrode (120) and a drain electrode (130) respectively positioned at two ends of the channel layer. An insulating film is positioned on another substrate. A heterojunction-based multilayer channel is formed by sequentially stacking a lower semiconductor material layer, a graphene layer (250) and an upper semiconductor layer on the insulating layer. The semiconductor material layer is silicon, gallium arsenide, germanium, molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, indium selenide, and black phosphorus. USE - Ternary logic device by connecting a conventional transistor and a graphene varistor including a heterojunction-based multilayer channel. ADVANTAGE - The operating performance of the ternary logic device is improved. The three logic states are expressed using the graphene-based heterojunction multi-layered channel. The bulk amounts of information is processed at high speed over the same area and time. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a ternary logic device. Substrate (110) Source electrode (120) Drain electrode (130) Channel layer (140) Graphene layer (250)