▎ 摘　　要

NOVELTY - The device has a two-dimensional (2D) material channel layer (110) arranged on a substrate (100), where a 2D material passivation layer is arranged on the 2D material channel layer. Multiple source/drain contacts are arranged on the 2D material passivation layer, where a gate structure is arranged on the 2D material passivation layer and between the source/drain contacts. A charge storage layer is arranged on the 2D material passivation layer, wherein the charge storage layer is narrower than the 2D material passivation layer. The gate structure comprises a gate dielectric layer, where a gate electrode is arranged on the gate dielectric layer. USE - Semiconductor device e.g. memory device or transistor (all claimed). ADVANTAGE - The device has high manufacturing efficiency and low manufacturing associated costs and small size. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for: (1) a memory device; and (2) a method for manufacturing a semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a semiconductor device. 100Semiconductor device 1102D material channel layer 110CHChannel region 120Material layer M1Patterned mask