▎ 摘　　要

NOVELTY - The semiconductor device has a substrate (10), a first graphene wire (20a), a second graphene wire (20b), a lower-layer contact (15) and an upper layer contact (33). The second graphene wire is formed on the same layer as the first multi-layered graphene wire above the substrate. The second graphene wire includes a multi-layered graphene layer into which the impurity is not doped. The lower-layer contact is connected to the undersurface side of the first multi-layered graphene wire. The upper-layer contact is connected to the upper surface side of the second multi-layered graphene wire. USE - Semiconductor device. ADVANTAGE - Reduces the wiring resistance in which the edge section of the second multi-layered graphene wire is doped since the doping process can be simplified without using the mask, e.g., photoresist film. Improves element characteristic since the resistance of the graphene wiring structure can be reduced without causing etching and corrosion of the metal material. Enables the process to be simplified and reduces the cost of the manufacturing process since doping can be performed at the patterning time of the multilayered wiring structure by selection of gas. Allows for effective selection of doping process for the respective regions since the number of wires connected to the lower-layer contacts is large in the memory cell region and the number of wires connected to the upper-layer contacts is large in the peripheral circuit region. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a semiconductor device manufacturing method. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of the structure of the semiconductor device. Substrate (10) Lower-layer contact (15) First graphene wire (20a) Second graphene wire (20b) Upper layer contact (33)