▎ 摘　　要

NOVELTY - A hybrid integrated optoelectronic chip of gallium nitride and graphene comprises chip main body and passivation layer that covers the chip main body. The chip main body comprises substrate, first coil metal layer, Schottky contact metal layer, Schottky diode, capacitor bottom electrode metal layer, first dielectric isolation layer, second dielectric isolation layer, upper electrode metal layer of capacitor, light emitting diode, bottom metal layer, second coil metal layer, and graphene layer. The first coil metal layer, Schottky diode and light emitting diode are all arranged on the substrate. The Schottky contact metal layer is disposed on the substrate between first coil metal layer and Schottky diode. The lower electrode metal layer of the capacitor is disposed on the substrate and extend to the surface of Schottky diode. The upper electrode metal layer of capacitor is arranged on the first dielectric isolation layer. USE - Hybrid integrated optoelectronic chip of gallium nitride and graphene. ADVANTAGE - The manufacturing cost of the integrated photoelectric chip is reduced. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for preparation of the optoelectronic chip comprising providing substrate, defining first to fifth areas, fabricating Schottky diode on substrate in the second area, fabricating light emitting diode in fourth area, forming Schottky contact metal layer on substrate and on Schottky diode between first area and second area, and forming Schottky contact between Schottky contact metal layer and Schottky diode; fabricating capacitor lower electrode metal layer on Schottky diode and one substrate in the third area, fabricating bottom metal layer on the substrate in fifth region and light emitting diode, and fabricating first dielectric isolation layer on metal layer of lower electrode of the capacitor and on substrate between third area and fourth area; fabricating second dielectric isolation layer on bottom metal layer of fifth region; fabricating capacitor upper electrode metal layer on the light-emitting diode on, first dielectric isolation layer and on substrate between the third area and fourth area, fabricating first coil metal layer on substrate in the first area, connecting end of first coil metal layer with Schottky diode to form a metal layer, forming second coil metal layer on second dielectric isolation layer; and forming a graphene layer on the bottom metal layer and on the second coil metal layer to obtain chip body, and forming passivation layer.