• 专利标题:   Semiconductor structure manufacturing method, involves forming interlayer medium layer on contact hole of metal-graphene, and filling electric conduction material in contact hole.
  • 专利号:   CN104282541-A, CN104282541-B
  • 发明人:   LIANG Q, YE T, ZHU H, ZHONG H
  • 专利权人:   INST MICROELECTRONICS CHINESE ACAD SCI, INST MICROELECTRONICS CHINESE ACAD SCI
  • 国际专利分类:   H01L021/28, H01L021/336, H01L029/45, H01L029/78
  • 专利详细信息:   CN104282541-A 14 Jan 2015 H01L-021/28 201520 Pages: 11 Chinese
  • 申请详细信息:   CN104282541-A CN10282657 06 Jul 2013
  • 优先权号:   CN10282657

▎ 摘  要

NOVELTY - The method involves providing a substrate (100). A shallow trench isolation structure is formed in the substrate and an active area. Metal-graphene (200) is formed on a surface of the substrate. A gate is formed at the metal-graphene. A metal-graphene layer is formed under the gate. A gate stack is formed, where the gate stack comprises a gate medium layer (210) and a gate electrode (250). An interlayer medium layer is formed on a contact hole (600) of the metal-graphene. An electric conduction material is filled in the contact hole. USE - Semiconductor structure manufacturing method. ADVANTAGE - The method enables reducing source/drain area contact resistance. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a semiconductor structure. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a semiconductor structure. Substrate (100) Metal-graphene (200) Gate medium layer (210) Gate electrode (250) Contact hole (600)