• 专利标题:   Electronic device for field effect transistor, comprises body including single crystal region that has hexagonal crystal lattice substantially lattice-matched to graphene, and epitaxial layer of graphene disposed on the region.
  • 专利号:   US2007187694-A1, WO2007097938-A1, KR2008100430-A, EP1984941-A1, JP2009527127-W, IN200804130-P4, US7619257-B2, CN101385126-A, CN101385126-B, JP5265385-B2, KR1351691-B1, EP1984941-B1
  • 发明人:   PFEIFFER L N, PFEIFFER L
  • 专利权人:   PFEIFFER L N, LUCENT TECHNOLOGIES INC, LUCENT TECHNOLOGIES INC, ALCATELLUCENT USA INC, LUCENT TECHNOLOGIES INC, ALCATELLUCENT USA INC, ALCATELLUCENT USA INC, PROVENANCE ASSET GROUP LLC
  • 国际专利分类:   H01L029/15, H01L021/20, H01L021/336, H01L029/78, C01B021/064, C01B031/04, C30B025/20, C30B029/02, H01L021/203, H01L021/205, H01L029/201, H01L029/786, H01L029/778, H01L029/16
  • 专利详细信息:   US2007187694-A1 16 Aug 2007 H01L-029/15 200767 Pages: 7 English
  • 申请详细信息:   US2007187694-A1 US355360 16 Feb 2006
  • 优先权号:   US355360, KR719823, CN80005630

▎ 摘  要

NOVELTY - An electronic device comprises a body including a single crystal region on its major surface. The single crystal region has a hexagonal crystal lattice substantially lattice-matched to graphene. At least one epitaxial layer (44) of graphene is disposed on the single crystal region. The surface region comprises a multi-layered single crystal hexagonal boron nitride or a wide band gap semiconductor. The graphene layer is deposited by molecular beam epitaxy from a vitreous carbon source, or by chemical vapor deposition. USE - For FET. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for: (1) field effect transistor (FET) (40) comprising a channel region coupling source and drain regions to one another, a gate region for applying voltage to the channel region to control the flow of current between the source in drain regions, and the electronic device, where the channel region includes a portion of the graphene layer; and (2) method of making the electronic device. DESCRIPTION OF DRAWING(S) - The figure is a schematic, top view of FET. FET (40) Insulative layer (42) Graphene Layer (44) Insulator region (48) Gate electrode (49)