• 专利标题:   Fabricating semiconductor structure, comprises providing substrate, forming fins on substrate, forming isolation structure layer having isolation structures, forming first opening by etching isolation structure and forming power rail.
  • 专利号:   US2021125987-A1, CN112701082-A, US11600619-B2
  • 发明人:   ZHANG H, LIU P
  • 专利权人:   SEMICONDUCTOR MFG INT SHANGHAI CORP, SEMICONDUCTOR MFG INT BEIJING CORP, SEMICONDUCTOR MFG INT BEIJING CORP
  • 国际专利分类:   H01L021/321, H01L021/3213, H01L021/8234, H01L027/092, H01L029/66, H01L029/78, H01L021/768, H01L023/528
  • 专利详细信息:   US2021125987-A1 29 Apr 2021 H01L-027/092 202148 English
  • 申请详细信息:   US2021125987-A1 US034129 28 Sep 2020
  • 优先权号:   CN11012609

▎ 摘  要

NOVELTY - Fabricating semiconductor structure, comprises: providing substrate (100); forming fins (110) on substrate; forming isolation structure layer (200) having isolation structures (200a), each isolation structure formed between fins; forming first opening by etching at least one isolation structure of structures and portion of substrate; and forming power rail by filling first opening with conductive material, where top surface of power rail is lower than top surface of fins. The conductive material is made of ruthenium, copper and/or graphene. The first mask layer is made of material i.e. silicon nitride, aluminum nitride, and/or silicon carbide. The second mask layer is made of hydrocarbon polymer. The conductive material layer is etched by dry etching process having process parameters including etching gas, i.e. carbon tetrafluoride, boron trichloride, oxygen, chlorine and/or helium. The metal layer is made of metal material having cobalt, tungsten, copper, ruthenium and/or platinum. USE - The method is useful for fabricating semiconductor structure. ADVANTAGE - The method: utilizes ruthenium has desirable electrical conductivity, high temperature and corrosion resistance, and excellent electrical performance; performs same response speed, dimension of standard cell may be reduced or under same dimension of standard cell, space may be available for wiring traces, thus improving response speed of semiconductor structure; improves semiconductor device performance, dimension of standard cell is increased to provide more space for wiring traces; and improves response speed of integrated circuit, dimension of standard cell needs to be enlarged to provide larger wiring trace space. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for semiconductor structure. DESCRIPTION OF DRAWING(S) - The figure shows cross-sectional view of the forming semiconductor structure. Substrate (100) Fins (110) Isolation structure layer (200) Isolation structures (200a)