▎ 摘　　要

NOVELTY - A graphene nanoribbon array is fabricated by (A) selectively seeding growth of graphene flakes (14) on substrate (10), including (A1) depositing poly(methyl methacrylate) (PMMA) dots on substrate in an mx n grid, where a periodicity of the grid is controlled by an initial spacing of PMMA dots on substrate, and (A2) depositing graphene on PMMA dots and substrate, where size of graphene flakes is controlled by controlling growth time of graphene flakes on PMMA dots; (B) masking graphene flake edges with a layer of insulator; (C) etching graphene flakes; (D) removing insulator to expose an mx n array of graphene nanoribbons having a set of facets when viewed in top plan; (E) etching greater than or equal to 1 electrode in each of the facets; and (F) providing a back plane to establish a graphene nanotransistor in each facet of each graphene nanoribbon. USE - Fabrication of graphene nanoribbon array for graphene nanotransistor grid manufacture (claimed). ADVANTAGE - The method is an improvement over current silicon complementary metal-oxide-semiconductor (CMOS) processing because it can scale down to smaller dimensions. With smaller digital transistors, packing density can be increased in next generation processors, making them faster and less expensive. The method provides a pathway for large scale manufacturing of graphene transistors with an intrinsic band gap for digital computing. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram of flakes after graphene has been deposited, and graphene flakes are given more time to grow. Substrate (10) Graphene flakes (14)