▎ 摘　　要

NOVELTY - The device has a gate oxide layer (3) which is arranged on the inner wall and the bottom of the trench, and polysilicon is filled in the gate oxide layer to form a polysilicon gate (4). A passivation layer (8) is arranged on the polysilicon gate and is used to isolate the polysilicon gate and the source metal (9). A graphene layer (12) is arranged outside the sidewall of the gate oxide layer. A P-type shielding layer (11) is arranged under the bottom of the graphene layer and the gate oxide layer. The passivation layer extends outward and covers the top of the graphene layer. USE - Trench silicon carbide power device. ADVANTAGE - The shield under the graphene layer shields the current flowing through the graphene layer during the off state of the device, thus improving the turn-off characteristics of the device. The electric field under the graphene layer is shielded to prevent the main carriers of the graphene layer from being converted into holes by electrons, thus improving the shutdown characteristics of the device. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for manufacturing trench silicon carbide power device. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view showing the cell structure of the low on-resistance trench silicon carbide power semiconductor device. Gate oxide layer (3) Polysilicon gate (4) Passivation layer (8) Source metal (9) P-type shielding layer (11) Graphene layer (12)