• 专利标题:   Integrated assembly for semiconductor device, has upwardly-extending structure comprising first insulative material, two-dimensional material, first electrostatic-doping-material, second insulative material and conductive-gate-structure.
  • 专利号:   US2022069133-A1, CN114121957-A
  • 发明人:   SANDHU G S, HILL R J, HWANG D K
  • 专利权人:   MICRON TECHNOLOGY INC, MICRON TECHNOLOGY INC
  • 国际专利分类:   H01L027/12, H01L029/423, H01L029/786, H01L021/8242, H01L027/108, H01L027/11507
  • 专利详细信息:   US2022069133-A1 03 Mar 2022 H01L-029/786 202233 English
  • 申请详细信息:   US2022069133-A1 US005054 27 Aug 2020
  • 优先权号:   US005054

▎ 摘  要

NOVELTY - Integrated assembly has an upwardly-extending structure comprising a first insulative material and having a pair of sidewall surfaces along a cross-section, and a top surface extending between the sidewall surfaces, two-dimensional-material adjacent the first sidewall surface, extending along the first sidewall surface, and having a lower region, an upper region, and a central region between the upper and lower regions, first electrostatic-doping-material adjacent the lower region of the two-dimensional-material, second insulative material adjacent the central region of the two-dimensional-material and on an opposing side of the two-dimensional-material from the first sidewall surface of the upwardly-extending structure, a conductive-gate-structure over the first electrostatic-doping-material, adjacent the second insulative material, and proximate the central region of the two-dimensional-material, and second electrostatic-doping-material over the conductive-gate-structure. USE - Integrated assembly for semiconductor device. ADVANTAGE - The integrated assembly has desired carrier properties to the source or drain regions. DETAILED DESCRIPTION - Integrated assembly has an upwardly-extending structure comprising a first insulative material and having a pair of sidewall surfaces along a cross-section, and a top surface extending between the sidewall surfaces, two-dimensional-material 24 adjacent the first sidewall surface, extending along the first sidewall surface, and having a lower region, an upper region, and a central region between the upper and lower regions, first electrostatic-doping-material 32 adjacent the lower region of the two-dimensional-material, second insulative material adjacent the central region of the two-dimensional-material and on an opposing side of the two-dimensional-material from the first sidewall surface of the upwardly-extending structure, a conductive-gate-structure over the first electrostatic-doping-material, adjacent the second insulative material, and proximate the central region of the two-dimensional-material, and second electrostatic-doping-material over the conductive-gate-structure and adjacent the upper region of the two-dimensional-material, where the sidewall surfaces are a first sidewall surface and the other of the sidewall surfaces are a second sidewall surface. An INDEPENDENT CLAIM is included for a method of forming the integrated assembly, which involves: a. forming first structures extending upwardly from a substrate; b. forming two-dimensional-material along an upper surface of the substrate within the gaps, and along outer peripheries of the first structures; c. forming first electrostatic-doping-material over the substrate and adjacent lower regions of the two-dimensional-material adjacent the first structures; d. forming insulative material over the first electrostatic-doping-material and adjacent central regions of the two-dimensional-material adjacent the first structures; e. forming conductive-gate-structure over the first electrostatic-doping-material and adjacent the insulative material; and f. forming second electrostatic-doping-material over the conductive-gate-structure and over the second insulative material. DESCRIPTION OF DRAWING(S) - The drawing shows diagrammatic cross-sectional side view of a region of an integrated assembly. Two-dimensional-material (24) Electrostatic-doping-materials (32) Upper electrostatic-doping-material (44) Source or drain regions (52, 54) Memory arrays (60)