▎ 摘　　要

NOVELTY - The structure has a silicon carbide fin (60) located on a surface of a silicon carbide-on-insulator substrate. A graphene nanoribbon (62) is located on a bare sidewall of the silicon carbide fin. A gate structure (65) is oriented perpendicular to the silicon carbide fin. The gate structure overlaps a portion of the graphene nanoribbon, and is located atop a portion of the silicon carbide fin. The portion of the graphene nanoribbon overlapped by the gate structure defines a channel region of the structure. The graphene nanoribbon has width defined by height of the silicon carbide fin. USE - Semiconductor structure e.g. dual-channel finFET, double-gate FET, and gate-all-round carbon nanotube FET. ADVANTAGE - The structure performs optional thinning process to reduce thickness of the silicon carbide substrate, and forms nanoribbons with uniform and potentially undamaged edges, and avoids line edge roughness, thus reducing deterioration of electrical quality. DETAILED DESCRIPTION - The structure includes a source region and a drain region made of metal carbide. An INDEPENDENT CLAIM is also included for a method for forming a semiconductor structure. DESCRIPTION OF DRAWING(S) - The drawing shows a perspective view of a semiconductor structure after forming a gate structure including a gate dielectric and a gate conductor. Handle substrate (52) Buried insulating layer (54) Silicon carbide fin (60) Graphene nanoribbon (62) Gate structure (65)