▎ 摘　　要

NOVELTY - An electronic component (100) is produced by (i) providing a substrate operable as a first electrode (102) having a surface, disposed in a deposition chamber, (ii) forming an anchoring layer (103) on the surface by serially exposing the substrate to first and second reactants in an atomic layer deposition process, where the atomic layer deposition process ends with exposing the substrate to first reactant to form a reactive surface, and (iii) forming a molecular layer (104) atop of the reactive surface employing physical vapor deposition of greater than or equal to 1 compounds, where greater than or equal to 1 compounds are of flexible conformation and have a conformation-flexible molecular dipole moment and a reactive anchoring group G configured to react with the reactive layer. USE - Production of electronic component e.g., resistive memory element (all claimed). ADVANTAGE - The method yields a molecular layer with high purity since the molecular layer is deposited as a portion of an atomic layer deposition (ALD) process, thus, contamination of the substrate surface by airborne volatile organic compounds and by impurities or decomposition products in a solvent is avoided. The method has high efficiency as no change of tool with breaking of vacuum is required between ALD step and deposition of a molecular layer. Annealing step is unnecessary and process robustness is improved. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for: (1) layer stack comprising a bottom layer operable as first electrode (102) and switchable molecular layer (104); (2) electronic component comprising layer stack comprising a substrate (101), a bottom layer operable as first electrode, anchoring layer (103) formed using atomic layer deposition; a switchable molecular layer formed using physical vapor deposition, and a second electrode (105) in contact with the molecular layer and optionally a top layer; and (3) compound selected from formulae R1A-(A1-Z1)r-B1-(Z2-A2)s-SpA-O-C(O)-O-R2 (IA-1), D1-ZD-(A1-Z1)r-B1-(Z2-A2)s-Sp-O-C(O)-O-R2 (IB-1) and R1C'-(A1-Z1)r-B1-ZL-A2C'-(Z3-A3)s-SpC-O-C(O)-O-R2 (IC-1). DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the layer structure of non-volatile memory element. Substrate (101) First electrode (102) Anchoring layer (103) Switchable molecular layer (104) Second electrode (105)