• 专利标题:   Method for forming fin FET, involves forming isolation region covering catalytic material layer, forming graphene nanoribbon on catalytic material layer on upper portion of semiconductor fin, and forming gate structure on nanoribbon.
  • 专利号:   EP3264472-A1, US2018006031-A1, CN107564818-A, US10361196-B2
  • 发明人:   ZHOU M
  • 专利权人:   SEMICONDUCTOR MFG INT SHANGHAI CORP, SEMICONDUCTOR MFG INT BEIJING CORP, SEMICONDUCTOR MFG INT SHANGHAI CORP, SEMICONDUCTOR MFG INT BEIJING CORP, SEMICONDUCTOR MFG INT BEIJING CORP
  • 国际专利分类:   H01L029/66, H01L029/78, H01L021/285, H01L021/762, H01L027/088, H01L029/16, H01L029/40, H01L021/28, H01L021/336
  • 专利详细信息:   EP3264472-A1 03 Jan 2018 H01L-029/66 201803 Pages: 13 English
  • 申请详细信息:   EP3264472-A1 EP178739 29 Jun 2017
  • 优先权号:   CN10512145

▎ 摘  要

NOVELTY - The method involves providing a substrate structure, where the substrate structure includes a semiconductor substrate and a semiconductor fin on the substrate (102). A catalytic material layer overlying the semiconductor fins is formed (104), where each semiconductor fin is configured as a back gate. An isolation region covering the catalytic material layer is formed (106) in a lower portion of the semiconductor fins. A graphene nanoribbon on the catalytic material layer is formed (108) on an upper portion of the semiconductor fin. A gate structure is formed (110) on the graphene nanoribbon. USE - Method for forming a semiconductor device i.e. fin FET. ADVANTAGE - The method enables increasing carrier mobility to improve the performance of a fin FET device. The method enables utilizing the fin FET device to provide good gate control capability. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart illustrating a method for manufacturing a semiconductor device. Step for providing substrate structure (102) Step for forming catalytic material layer overlying semiconductor fins (104) Step for forming isolation region covering catalytic material layer in lower portion of semiconductor fins (106) Step for forming graphene nanoribbon on catalytic material layer on upper portion of semiconductor fin (108) Step for forming gate structure on graphene nanoribbon (110)