▎ 摘　　要

NOVELTY - A three-dimensional integrated circuit (100) comprises a second gate stack portion disposed on a second dielectric layer formed on a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate; and including a graphene layer. USE - A three-dimensional integrated circuit. ADVANTAGE - The circuit has high frequency and charge carrier mobility. DETAILED DESCRIPTION - A three-dimensional integrated circuit (100) comprises: (A) a silicon substrate; (B) a first source region disposed on the substrate; (C) a first drain region disposed on the substrate; (D) a first gate stack portion disposed on the substrate; (E) a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate; (F) a second dielectric layer formed on the first dielectric layer; (G) a second source region disposed on the second dielectric layer; (H) a second drain region disposed on the second dielectric layer; and (I) a second gate stack portion disposed on the second dielectric layer, and including a graphene layer. DESCRIPTION OF DRAWING(S) - The drawing is a schematic sectional view of a 3-Dimensional hybrid integrated circuit including a top-gated graphene Field Effect Transistor. Three-dimensional integrated circuit (100) Top-gated graphene field effect transistor device (103) Electric layers (111, 124) Gate stack (120) Conductive gate material (126)