▎ 摘　　要

NOVELTY - A layer of graphene (102) is deposited on a substrate (104), and layer of amorphous silicon (106a) deposited on graphene layer having upper and lower layers. The upper layer of amorphous silicon layer is converted into a gate dielectric layer (108). Source and drain contact regions (110) are formed in contact with graphene layer. A gate electrode (112) is formed on dielectric layer between source and drain contact regions, and graphene device is formed. USE - Formation of graphene device e.g. logic device and analog device for field effect transistor. ADVANTAGE - The graphene device has high speed and durability. The gate dielectric layer having high quality and low leakage and trap density is formed. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for buried channel graphene device. DESCRIPTION OF DRAWING(S) - The drawing shows the schematic view explaining manufacture of field effect transistor. Graphene layer (102) Substrate (104) Amorphous silicon layer (106a) Dielectric layer (108) Source-drain contact regions (110) Gate electrode (112)