• 专利标题:   Large-scale graphene-containing chip multiprocessor, has additional processor cores placed on die, where high-speed processor cores operate when some of additional processor cores are configured to be gated.
  • 专利号:   WO2015023277-A2, TW201523438-A, WO2015023277-A3, US2016232127-A1, CN105830046-A, TW536260-B1, US10095658-B2
  • 发明人:   POTKONJAK M
  • 专利权人:   EMPIRE TECHNOLOGY DEV LLC, ENPAL TECHNOLOGY DEV CO LTD, EMPIRE TECHNOLOGY DEV LLC
  • 国际专利分类:   G06F015/16, G06F009/28, G06F009/46, G06F015/80, G06F009/52, G06F001/32, G06F009/50, H01L029/16, H01L029/165
  • 专利详细信息:   WO2015023277-A2 19 Feb 2015 G06F-015/16 201515 Pages: 49 English
  • 申请详细信息:   WO2015023277-A2 WOUS055025 15 Aug 2013
  • 优先权号:   CN80078893, WOUS055025, US14411917, CN80078893

▎ 摘  要

NOVELTY - The multiprocessor has high-speed processor cores placed on a die and including graphene-containing computing elements. A set of additional processor cores is placed on the die, and includes lower percentage of graphene-containing computing elements than the high-speed processor cores. The high-speed processor cores operate when some of the additional processor cores are configured to be gated. A task manager is coupled to first, second and third processor groups, and selects the processor groups for operation based on a level of parallelism of an application. USE - Large-scale graphene-containing chip multiprocessor. ADVANTAGE - The multiprocessor allows specific computing elements of graphene-containing processor core to be formed with graphene, so that the computing elements can be selected to improve performance of the graphene-containing processor core while minimizing or reducing leakage energy of the graphene-containing processor core. The multiprocessor utilizes a same group of processors for all blocks of software application, so that context switching costs can be avoided. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for scheduling instructions to be processed by a chip multiprocessor. DESCRIPTION OF DRAWING(S) - The drawing shows a flow diagram illustrating a method for scheduling instructions for processing by a chip multiprocessor that includes graphene-containing computing elements. Method for scheduling instructions for processing by chip multiprocessor (600) Step for determining cost and energy cost for processing first block of instructions (601) Step for selecting first processor group to execute first block of instructions (602) Step for determining cost and energy cost for processing second block of instructions (603) Step for selecting second processor group to execute second block of instructions (604)