▎ 摘　　要

NOVELTY - Semiconductor package (200) comprises: a package substrate (210); semiconductor devices (202) disposed over the package substrate; a package ring (240) disposed on a perimeter of the package substrate, surrounding the semiconductor devices; a cover (250) comprising silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover. The TIS comprises: a first solder layer bonded to the semiconductor devices and comprising germanium; and an interface layer disposed on the first solder layer. The first and second solder layers comprise one of germanium, indium, or tin. The interface layer comprises an indium foil. The interface layer comprises one of carbon nanotubes, a graphene composite, and/or a silver paste. USE - The package is useful: in integration density of various electronic components e.g. transistors, diodes, resistors, and capacitors; as quad flat pack, pin grid array, ball grid array, flip chips, three-dimensional integrated circuits, wafer level packages, package on package, system on chip or system on integrated circuit devices. ADVANTAGE - The package utilizes: TIS which has a thermal resistance of (≤5℃.*mm2)/W; has a thermal design power of at least 2000 Watts; and thermal interface structures which reduce the amount of thermal-mechanical stress applied to the semiconductor packages, without the need for the additional backside metallization. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for manufacturing the semiconductor package. DESCRIPTION OF DRAWING(S) - The figure illustrates simplified top view of semiconductor package. 200Semiconductor package 202Semiconductor devices 210Package substrate 240Package ring 250Cover