▎ 摘　　要

NOVELTY - The method involves forming an opening in resist between a source electrode (102) and drain electrode. A gate electrode (124) with head and foot regions is formed in opening. The foot region is in contact with primary portion of a thin film (106) in a channel area (134). A dielectric layer is formed on outer surface of gate electrode. Metal layers are deposited over source and drain electrodes, head region of gate electrode and secondary portion of thin film. The deposition of metal layer over tertiary portion of thin film proximate foot region is inhibited by head region. USE - Method for manufacturing FET such as self-aligned graphene FET for graphene device (all claimed). ADVANTAGE - The parasitic resistance can be reduced by increasing the height of the T-shaped electrode. The scalable, registration-free fabrication and integration of nanomaterials into FETs can be allowed efficiently and cost-effectively by preparing large-area nanomaterial thin films. The adhesion between nanotubes in the nanotube solution and the substrate can be improved efficiently. The gate resistance can be readily reduced by increasing the cross-sectional area of the head of T-shaped gate electrode. Thus the improvement in the power gain of high frequency FETs can be achieved. The misalignment can be eliminated. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for FET. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view illustrating the process of fabrication of self-aligned FET with T-shaped gate electrode. FET (100) Source electrode (102) Thin film (106) Gate electrode (124) Channel area (134)