• 专利标题:   Preparation of reduced and N-doped graphene oxide used in a transistor, comprises preparing mixed solution containing graphene oxide and tetramethylammonium hydroxide, and heating the mixed solution.
  • 专利号:   US2016315194-A1, KR2016127252-A, KR1739347-B1, US9893199-B2
  • 发明人:   KHAN F, BAEK S, KIM J H, BAEK S H
  • 专利权人:   DAEGU GYEONGBUK INST SCI TECHNOLOGY, DAEGU GYEONGBUK INST SCI TECHNOLOGY
  • 国际专利分类:   H01L029/24, H01L029/423, H01L029/49, H01L029/51, H01L029/786, C01B031/04, H01L051/00, C01B032/182, H01L029/16, H01L029/778
  • 专利详细信息:   US2016315194-A1 27 Oct 2016 H01L-029/786 201675 Pages: 16 English
  • 申请详细信息:   US2016315194-A1 US966700 11 Dec 2015
  • 优先权号:   KR057963

▎ 摘  要

NOVELTY - Preparation of reduced and N-doped graphene oxide (4), comprises: (a) preparing the mixed solution containing graphene oxide and tetramethylammonium hydroxide; and (b) heating the mixed solution. USE - The method is useful for preparation of reduced and N-doped graphene oxide, used in a transistor (claimed) including FET. ADVANTAGE - The method: does not require any additional additive: is simple and pro-environmental method; and provides mass production of reduced and N-doped graphene oxide at low temperatures in cost-effective manner. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a transistor (100) which is located on top of the reduced and N-doped graphene oxide prepared by the method, in the structure composed of a gate electrode (3), a gate insulator (1) on top of the gate electrode, a semiconductor oxide (2) on top of the gate insulator, and the reduced and N-doped graphene oxide on top of the semiconductor oxide, and contains a source electrode and a drain electrode facing each other. DESCRIPTION OF DRAWING(S) - The figure illustrates the transistor containing the reduced and N-doped graphene oxide. Gate insulator (1) Semiconductor oxide (2) Gate electrode (3) Reduced and N-doped graphene oxide (4) Transistor (100)