• 专利标题:   Method for preparing gate self-aligned vertical nano air channel bipolar junction transistor, involves forming dielectric layer on substrate and mesa, and exposing portion of substrate window as drain or source.
  • 专利号:   CN114512380-A, CN114512380-B
  • 发明人:   JIANG H, YANG F, ZHAO H, HUANG R, WANG J, ZHAO J, WEI Y, ZHANG J, LI M, CHEN F
  • 专利权人:   UNIV CHINA ELECTRONIC SCI TECHNOLOGY
  • 国际专利分类:   H01J009/02
  • 专利详细信息:   CN114512380-A 17 May 2022 H01J-009/02 202258 Chinese
  • 申请详细信息:   CN114512380-A CN10104288 28 Jan 2022
  • 优先权号:   CN10104288

▎ 摘  要

NOVELTY - The method involves forming a first mesa on a substrate (10), where a first dielectric layer is located between a first conductive layer (11) and the substrate. A dielectric layer (121) is formed on the substrate and the first and second mesa. A portion of the substrate window is exposed as a drain or a source (12A) and a dielectric layer and a second table board are formed on the substrate so as to expose a portion of a substrate window to be used as a drain electrode or a source electrode and the second mesa includes a second conductive layer (122). The lower part of the second conducting layer is used as a drain electrode or a source electrode (22A), and a nano air channel is formed by wet etching to finish the preparation of the vertical nano air channel triode. The first conductive layer and the second conductive layer are made of metal, transparent conductive film, graphene, doped semiconductor thin film, or metalloid. USE - Method for preparing gate self-aligned vertical nano air channel bipolar junction transistor used in power amplifier, logic circuit, and drive circuit. ADVANTAGE - The method uses common UV lithography and coating process, which can quickly and conveniently realize large area wafer level nano air channel bipolar junction transistor the batch preparation by controlling the thickness of the plating film can accurately control the length of the nano- air channel and the distance between the gate and the source and drain electrode and the relative position, it has simple operation, high yield, good process consistency and good repeatability. The method does not need alignment, and does not depend on high nanometer processing device, low cost, and high yield. DESCRIPTION OF DRAWING(S) - The drawing shows a process flow diagram of the method for fabricating gate self-aligned vertical nano air channel triode based on a lift-off process. (Drawing includes non-English language text). Insulating substrate (10) First conductive layer (11) Metal source or drain (12A) Source electrode (22A) Dielectric layer (121) Second conductive layer (122)