• 专利标题:   Method for preparing graphene-based FET, involves forming metal electrode on substrate exposing sub ion-doped region to obtain graphene-based FET, and etching silicon nitride dielectric layer and ring-shaped gate structure.
  • 专利号:   CN112599593-A, CN112599593-B
  • 发明人:   CHEN C, HE Z, ZHOU Q, WU D, JIANG S, SHI F
  • 专利权人:   UNIV SHANGHAI JIAOTONG
  • 国际专利分类:   H01L021/335, H01L021/67, H01L029/16, H01L029/423, H01L029/772
  • 专利详细信息:   CN112599593-A 02 Apr 2021 H01L-029/16 202137 Pages: 13 Chinese
  • 申请详细信息:   CN112599593-A CN11446473 11 Dec 2020
  • 优先权号:   CN11446473

▎ 摘  要

NOVELTY - The method involves forming (S106) a second ion doping region inside the sidewall structure through the second ion doping region forming module. An isolation layer is formed on the epitaxial layer where the second ion doped region is formed by the isolation layer forming module. The silicon nitride dielectric layer and the ring-shaped gate structure are etched (S107) through the metal electrode forming module. The second ion-doped region is exposed. A metal electrode is formed on the substrate exposing the second ion-doped region to obtain the graphene-based FET. The processing device is used to thin and thin the prepared graphene-based FET through the FET processing module. The finished product of the graphene-based FET is obtained. The polycrystalline silicon layer is etched to form the annular silicon gate structure. USE - Method for preparing graphene-based FET (claimed). ADVANTAGE - The planar area of the gate structure and the gate capacitor is reduced. The switching rate of the field effect transistor is effectively improved. The graphene surface is assembled with periodically arranged nano-micro-sphere array. The sensitivity of detection is improved. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a system for preparing graphene-based FET. DESCRIPTION OF DRAWING(S) - The drawing shows a flowchart illustrating a method for preparing graphene-based FET. (Drawing includes non-English language text) Step for forming a patterned mask composite layer on the epitaxial layer forming the annular gate structure by the first ion doped region forming module (S104) Step for forming a silicon nitride dielectric layer on the substrate forming the first ion doped region through the sidewall structure forming module (S105) Step for forming a second ion doping region inside the sidewall structure through the second ion doping region forming module (S106) Step for etching silicon nitride dielectric layer and the ring-shaped gate structure through the metal electrode forming module (S107) Step for obtaining finished product of the graphene-based FET (S108)