▎ 摘　　要

NOVELTY - The structure has a first wiring layer (13) that comprises a first bottom surface (131) and a first top surface (132), and is set on first solder layer (11). Several conductive through-hole columns (14) are set on the first wiring layer, and electrically connected with the first top surface. The second chip group (15) is set between conductive through hole columns. The second wiring layer (16) comprises a second bottom surface (161) and a second top surface (162). The second bottom surface is set on the conductive through hole column. The radiating element is set on the second top surface. The second solder layer (18) is set at the position where the second top surface is not installed with the radiating element. The third chip group (19) is set on the second solder layer, and electrically connected with the second wiring layer through the second solder layer. USE - Fan-out type packaging structure for packaging different types of chip and electronic components in system level for portable electronic product i.e. notebook computer, and used at high density and large power scene application. ADVANTAGE - The method enables setting the radiating element between the second wiring layer and the third chip group under the condition of occupying small space, thus improving radiating benefit of the fan-out type packaging structure at high density and large power scene application. The method allows a graphene heat plate and a multilayer stack to improve radiating efficiency of radiating array, so that the structure design of single chip is improved, thus increasing working efficiency of the single chip, and improving function integrity and application flexibility of the packaging structure. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a preparation method of fan-out type packaging structure. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of the fan-out type packaging structure radiating element. 11First solder layer 12First chip group 13First wiring layer 14Conductive through hole column 15Second chip group 16Second wiring layer 18Second solder layer 19Third chip group 21First packaging layer 22Filling layer 131First bottom surface 132First top surface 161Second bottom surface 162Second top surface 171Graphene substrate