• 专利标题:   Semiconductor element used in various integrated circuit devices, has substrate comprising trench, source region, and drain region, where source region and drain region separated apart from each other by trench, gate insulating layer covering bottom surface and sidewall of trench, gate electrode.
  • 专利号:   US2023072863-A1, KR2023036887-A
  • 发明人:   CHO Y, BYUN K, KIM S, LEE E, BYUN K E, CHO Y C
  • 专利权人:   SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO LTD
  • 国际专利分类:   H01L027/108, H01L029/08, H01L029/40, H01L029/423, H01L029/49, H01L029/66, H10B012/00
  • 专利详细信息:   US2023072863-A1 09 Mar 2023 H01L-027/108 202324 English
  • 申请详细信息:   US2023072863-A1 US939303 07 Sep 2022
  • 优先权号:   KR119932

▎ 摘  要

NOVELTY - Semiconductor element has substrate comprising a trench, a source region (71), and a drain region (72). The source region and a drain region separated apart from each other by the trench. A gate insulating layer covering a bottom surface and a sidewall of the trench. A gate electrode comprising a lower buried portion and an upper buried portion with the gate insulating layer around. The lower buried portion filling a lower region of the trench. The upper buried portion being on the lower buried portion and filling an upper region of the trench. S capping layer on the gate electrode. The lower buried portion (41) comprises a barrier layer and a first conductive layer. The barrier layer is in the trench. The barrier layer (31) covers a bottom surface of the gate insulating layer and a lower region of a sidewall of the gate insulating layer. The barrier layer surrounds the first conductive layer (32). The first conductive layer fills the lower region of the trench. USE - Semiconductor element used in various integrated circuit devices, such as memories, driving IC, logic devices. ADVANTAGE - The semiconductor element has effectively reduced gate induced drain leakage. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for: 1. an electronic system, which comprises: a controller, a memory configured to store instructions executed by the controller, the memory comprising the semiconductor element, and an input/output device coupled to the controller; and 2. a method of fabricating a semiconductor element, which involves: (a) forming a trench in a substrate; (b) forming a gate insulating layer to cover a bottom surface and a sidewall of the trench; (c) forming a gate electrode on the gate insulating layer in the trench; (d) forming a capping layer on the gate electrode; and (e) forming a source region and a drain region in the substrate respectively on both sides of the gate electrode, where the forming of the gate electrode comprises forming a barrier layer in the trench, forming a two-dimensional material layer in the trench, and forming a conductive layer in the trench, the barrier layer covers a bottom surface of the gate insulating layer and a lower region of a sidewall of the gate insulating layer, the two-dimensional material layer covers an upper region of the sidewall of the gate insulating layer, and the conductive layer is surrounded by the barrier layer and the two-dimensional material layer, an upper region of the conductive layer is surrounded by the two-dimensional material layer, a lower region of the conductive layer is surrounded by the barrier layer, and a work function of the upper region of the conductive layer is less than a work function of the lower region of the conductive layer. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a semiconductor element. 31Barrier layer 32First conductive layer 41Lower buried portion 71Source region 72Drain region